As AI infrastructure scales, I believe evaluating server network adapters solely by port speed or PCIe generation no longer tells the full story. Three factors are becoming increasingly important in shaping network architectures: performance, programmability, and power efficiency. Performance determines how efficiently data moves; programmability determines which infrastructure functions can execute outside the host CPU; and power efficiency influences system cost, cooling requirements, and deployment density.
According to Dell’Oro Group’s latest Ethernet Adapter & Smart NIC market forecast, the market is projected to grow to $53.6 B by 2030. As AI infrastructure investment accelerates, the more important question is not simply how fast the market will grow, but how evolving networking architectures will influence demand and competitive positioning across different adapter segments.
As illustrated in the accompanying chart, general-purpose (GP) NICs, Data Processing Units (DPUs) and Infrastructure Processing Units (IPUs), AI-optimized NICs, and emerging scale-up transport occupy different positions along the performance-programmability spectrum. These are conceptual distinctions, not a linear progression: actual capabilities overlap and depend on implementation.
The deeper market question is not simply which adapter is fastest. It is where networking functions should reside—and which capabilities customers will pay to accelerate, offload, or integrate within their power and thermal budgets.
Different Workloads, Different Value Propositions.
General-purpose NICs
Connectivity as the baseline. General-purpose NICs serve enterprise, cloud, and data center workloads requiring reliable connectivity, compatibility, and cost efficiency. Their capabilities vary in bandwidth and hardware offloads. Where conventional connectivity meets workload requirements, additional processing may not justify its incremental cost.
For vendors, opportunities remain in cost-effective, easy-to-deploy 10/25G and 100G general-purpose Ethernet adapters. According to our Ethernet Adapter & Smart NIC research, Ethernet adapters operating at 100 Gbps and below are projected to account for 86% of port shipments in 2030 across the front-end networks of enterprises, non-AI cloud providers, and telecom operators.
DPUs/IPUs
Programmable infrastructure offload. Data Processing Units (DPUs) and Infrastructure Processing Units (IPUs) are programmable processors designed to offload networking, security, storage, and other infrastructure functions from host CPUs. Depending on the implementation, they combine general-purpose processor cores with networking engines and dedicated hardware accelerators to support virtual switching, security, storage, and infrastructure management. In our Ethernet Adapter & Smart NIC research, DPUs and IPUs are categorized within the Smart NIC segment, and Smart NICs are projected to account for 83% of NIC port shipments in hyperscalers’ front-end networks by 2030. The hardware data path engine or packet pipeline of a DPU/IPU (Smart NIC) can be implemented using either fixed-function ASICs or reconfigurable Field Programmable Gate Arrays (FPGAs).
As agentic AI increases infrastructure complexity through multi-step reasoning, tool orchestration, memory access, and policy enforcement, DPUs/IPUs may offer new opportunities to offload selected networking, security, and infrastructure tasks. The key market question is whether these demands will drive broader DPU/IPU adoption beyond established cloud deployments, which customer segments will lead incremental demand, and whether programmable offload will expand the Smart NIC market or intensify competition with AI-optimized NICs.
AI-optimized NICs
Performance at scale. Distributed AI training and accelerator-intensive workloads require high effective bandwidth, efficient transport, congestion management, and predictable latency. Specialized adapters may accelerate RDMA, supported transport protocols, and selected collective-communication functions.
Power efficiency is equally important. Indicative profiles range from approximately 15–30 W for some 400G fixed-function adapters to 40–75 W for some 800G-and-higher designs. Actual consumption varies by implementation. As port speeds rise, SerDes and PHY circuitry can add to the power and cooling burden. The relevant metric is therefore not bandwidth alone, but effective networking performance per watt. Across large clusters, adapter power contributes to rack-level heat removal requirements and can constrain system design.
These categories differ in emphasis, not absolute capability. AI NICs can incorporate sophisticated acceleration, while DPUs/IPUs can also support high-throughput networking.
Scale-Up Networking: An Emerging Frontier for AI Infrastructure
The next architectural shift may extend beyond faster conventional adapters. Scale-out networking connects servers through a fabric. Scale-up networking extends high-performance communication across accelerators, potentially spanning multiple racks. Depending on the design, this can introduce requirements for accelerator-aware communication, memory semantics, and coordinated endpoint and transport behavior.
Open Compute Project initiatives, including Ethernet for Scale-Up Networking (ESUN) and Scale-Up Ethernet Transport (SUE-T), illustrate this direction.
If these architectures mature and achieve deployment at volume, networking functions could move closer to accelerator silicon or into tightly integrated packages. This could change the role of conventional adapters and redistribute value among accelerator vendors, network silicon suppliers, and system designers.
While on-die scale-up networking is not yet covered in our Ethernet Adapter & Smart NIC research, we are closely watching how these emerging architectures evolve. Interoperability, software maturity, manufacturing, and customer qualification will determine which approaches gain commercial traction. Integration may reduce some data-movement overheads, but system-level power savings must be demonstrated rather than assumed.
Three Market Developments Shaping Ethernet Adapters and Smart NICs
- System-level performance
Higher port speeds alone do not guarantee better workload performance. Improvements in accelerator utilization, job completion time, and total system cost provide stronger evidence of differentiation.
- Economics of programmable offload
DPUs/IPUs can consume substantially more power than fixed-function adapters because they incorporate general-purpose processing and additional acceleration logic. That cost may be justified when offloading infrastructure functions reduces host CPU demand or improves isolation. The right comparison is net system-level power and performance, not adapter power in isolation.
- Scale-up deployment at volume
Standards progress and product announcements matter, but interoperability, customer qualification, and repeatable deployments are stronger indicators of commercial adoption. Product leaders should also assess whether emerging architectures improve power efficiency and thermal density at the system level.
The Strategic Implication
The AI networking market is unlikely to converge on a single adapter architecture. General-purpose NICs, DPUs/IPUs, and AI-optimized adapters address different requirements, while emerging on-die scale-up designs may change where connectivity and transport functions reside.
The deeper shift is not simply toward faster networking, but toward a redistribution of networking functions across the computing system. For vendors and infrastructure providers, success will depend on identifying which functions warrant dedicated hardware, which require programmability, and which may be integrated into the accelerator or fabric. The winning designs will balance performance, programmability, and power efficiency to deliver measurable system-level value.
As these architectures evolve, understanding the adoption and market positioning of Ethernet Adapters and Smart NICs will become increasingly important.
